Covered - Reading Line Coverage
Author: Trevor Williams

|  |  | 18
User Manual - «Covered»
|  |  | 12.1 Reading Line Coverage
|  |  | 12.1.1 Summary Information Description - Module-based
|  |  | For module-based reports, the summary table for line metrics includes information for the name of each module that was covered and the name of the file in which the module is described in. Lines 18 through 22 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma and fsmb. The table shows that all three modules were described in the file "example.v".
|  |  | 12.1.2 Summary Information Description - Instance-based
|  |  | For instance-based reports, the summary table for line metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand-side of each row. Lines 18 through 22 of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1" and "main.fsm2".
|  |  | 12.1.3 Summary Information Description - Both
|  |  | On the right-hand side of each row in the table are the hit, miss and total numbers for the line coverage, followed by a calculated percent of the lines that were hit (calculated by taking the number of lines hit during simulation divided by the total number of lines that Covered simulated). The hit value indicates how many lines were executed during the simulation; the miss value indicates the number of lines not executed during simulation; and the total value indicates the total number of lines within the specified module/instance that Covered was able to simulate.
|  |  | If the percentage value in the far left of the summary table is 100%, this indicates that all lines that Covered was capable of simulating (for the module/instance of this row) were executed. If the value of the percentage is less than 100%, this indicates that some number of lines were not executed and full coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any lines in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%.
|  |  | 12.1.4 Verbose Information Description - Both
|  |  | If the miss value for a particular module was not 0 (indicating that lines were missed during simulation) and the '-d v' option was specified on the command-line (specifying to output verbose reporting information), the line that was missed during simulation will be output below the summary information per module that contained missed lines. In our sample report, there was one line that was missed during simulation (according to the summary output) for the module called "fsmb" (instance "main.fsmb"). The line number and Verilog line that was missed is output in lines 25 through 29 of the module-based report and in lines 25 through 29 of the instance-based report.
|  |  | If a module does not contain any missed lines and the '-d v' option was specified, no verbose output will be displayed for this module. Likewise, if a module/instance does not contain any lines that Covered could execute, no verbose output will be displayed.
|  |  | Important Note
|  |  | The definition of what Covered considers a line is a statement (ex. assignment, conditional, etc.). If a statement is written in such a way that it consumes multiple file lines, Covered only counts the statement as one line. The user can assume that if the beginning of a statement is labeled as missed, the entire expression was missed (not just the first line of the expression). For example, consider the following code:
          always @(posedge b)
            a <= (b & c) |
                 (d & e);
|  |  | If the expression
     a <= (b & c) | (d & e);
is not executed during simulation, Covered will indicate that only one line was missed during execution (not two), and it will display the missing line (if verbose reporting is specified with the '-d v' option) as the following:
         2:      assign a <= (b & c) ...
|  |  | The "..." notation at the end of the Verilog output indicates that the statement was a multiline statement in the source code but is only considered one line.
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