Covered - Line Coverage
Author: Trevor Williams

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User Manual - «Covered»
|  |  | 2.1 Line Coverage
|  |  | Line coverage simply answers the question, "Was this line of code executed during simulation?"
|  |  | Covered will display the number of logical lines of code that exist in a particular file with the number of logical lines that were executed during the simulation along with a percentage indicating the percentage of lines executed. If verbose mode is selected for a report, Covered will display the lines of logic that were not executed during the simulation run.
|  |  | 2.1.1 Example
| Example |  | Suppose that the following module was specified in your DUT that is being analyzed:
|  |  | module test; reg a, b, c; initial begin a = 0; // Line 1 b = 1; // Line 2 if( a ) c = b; // Line 3 else c = ~b; // Line 4 end endmodule
|  |  | If this code were simulated as stated, the simulator would execute lines 1 and 2, and due to the value assigned to `a`, line 4 would be executed. This means that during execution, out of a possibility of 4 lines, only 3 were executed. Therefore, Covered would state that for this module the line coverage percentage would be 75% (or 3 out of 4).
|  |  | 2.1.2 Recommendations
| Recommendations |  | For a design to pass full coverage, it is recommended that the line coverage for all modules in a design receive 100% coverage. If a line of logic is not executed during simulation, the design has not been fully exercised. Line coverage is useful for determining holes in the test suite.
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