Covered - Reading Combinational Logic Coverage
Author: Trevor Williams

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User Manual - «Covered»
|  |  | 12.3 Reading Combinational Logic Coverage
|  |  | 12.3.1 Summary Information Description - Module-based
|  |  | For module-based reports, the summary table for combinational logic metrics includes information for the name of each module that was covered and the name of the file in which the module is described in. Lines 87 through 92 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma, and fsmb. The table shows that all three modules were described in the file "example.v".
|  |  | 12.3.2 Summary Information Description - Instance-based
|  |  | For instance-based reports, the summary table for combinational logic metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand-side of each row. Lines 87 through 92 of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1", and "main.fsm2".
|  |  | 12.3.3 Summary Information Description - Both
|  |  | On the right-hand side of each row in the table are the hit, miss and total numbers for the combinational logic coverage, followed by a calculated percent of the combinational logic expression values that were hit (calculated by taking the number of combinational logic expression values hit during simulation divided by the total number of expression values that Covered could have simulated). The hit value indicates how many expression values were achieved during the simulation; the miss value indicates the number of expression values not achieved during simulation; and the total value indicates the total number of combinational logic expression values that could have been achieved in the specified module/instance.
|  |  | If the percentage value in the far left of the summary table is 100%, this indicates that all combinational logic expression values that Covered was capable of achieving (for the module/instance of this row) were hit. If the value of the percentage is less than 100%, this indicates that some number of expression values were not achieved and full coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any combinational logic expressions in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%.
|  |  | 12.3.4 Verbose Information Description - Both
|  |  | The verbose output for combinational coverage is a bit more sophisticated than the line or toggle. Basically, for each expression that was found to not be fully covered (either the expression itself or some sub-expression in the tree was not fully covered), the expression is output with various sub-expressions underlined and identified with a number. Each expression is also supplied with the line number that the expression started at in its module file. In our example, there is one uncovered expression in the module called "main" (see lines 95 through 134 (numbered 5) which contains four uncovered subexpressions (numbered 1 through 4).
|  |  | Below each expression, there will be one or more tables which specify a particular sub-expression that was not fully covered along with information describing what cases were not covered for that sub-expression.
|  |  | In the report output above, we see that there was one expression in module "main" that did not achieve 100% coverage that starts on line 14 of the Verilog source. The expression is output to the report with certain sub-expressions underlined and labeled with an integer value for reference.
|  |  | For this one expression, there were found to be four subexpressions (labeled 1, 2, 3, 4) that were found to not be 100% covered. Taking a look at subexpression 1 report output, the numbers to the right of the string "Expression 1" tell us the number of logical combinations of this subexpression that were hit (in this case 2 combinations were hit) and the total number of logical combinations that this subexpression can have (in this case 3 combinations were achievable). The character string below this information tells us the type of subexpression that we are examining. For subexpression 1, the type is the bitwise AND operator (&).
|  |  | The table below this information for subexpression 1, lists the potential combinations that this subexpression could have reached with a '*' character placed underneath the combination(s) that were missed. In the case of subexpression 1, the left and right subexpressions did not evaluate to values of 1 simultaneously The letter 'L' above each possible combination indicates the value that the left subexpression achieved at the same time as the value under the right subexpression indicated with the letter 'R'. Legal values for a subexpression are '0', '1' or '-' (which indicates that this subexpression value could either be 0 or 1).
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